The present invention relates to a semiconductor design technology, and more particularly to power mesh routing of a semiconductor memory device.
Semiconductor memory devices such as a DRAM receive data from a chipset (memory controller) for a write operation and output data to the chipset for a read operation. For synchronous semiconductor memory devices, both the chipset and the memories are synchronized with system clocks. However, while transferring the data and the system clocks from the chipset to the memories, a skew is generated between the data and the system clocks, because of the differences of loadings and traces between the data and the system clocks and the difference in locations of the memories.
To reduce the skew between the data and the system clock, the chipset transfers data to the memory together with a data strobe signal (DQS). The data strobe signal (DQS) is referred to as an echo clock, and has the same loading and trace as the data. Accordingly, by strobing the data using the data strobe signal at the memory, it is possible to minimize the skew caused by the reason described above. Meanwhile, during the read period, the memory transfers to the chipset the data together with a read data strobe signal.
FIG. 1 is a diagram illustrating a pad layout and a power mesh routing of a conventional synchronous semiconductor memory device. Referring to FIG. 1, the conventional synchronous semiconductor memory device includes a plurality of data input/output pads DQ0 to DQ7, data strobe signal pads DQS and DQSB, and a data mask pad DM, and a plurality of power pads VDDQ and VSSQ for a driver.
The data input/output pads DQ0 to DQ7 are disposed to either side of the data strobe signal pads DQS and DQSB. The power pads VDDQ and VSSQ for the driver are disposed at spaces between the data input/output pads DQ0 to DQ7 and the data strobe signal pads DQS and DQSB. For reference, the data strobe signal DQSB is a differential signal of the data strobe signal DQS.
The power pads VDDQ for a supply voltage and the power pads VSSQ for a ground voltage are connected to one another through respective power meshes 10 and 15. This is aimed to reduce the resistance to thereby smoothly adjust the chip power supply state to all the circuits.
However, such a structure for routing the power mesh causes a simultaneous switching output (SSO) noise and deterioration of AC characteristics such as tDQSQ and tDQSCK. The semiconductor memory device is under restraint in a high speed read operation. Here, the tDQSQ is a parameter representing a skew of the data strobe signal DQS and the data DQ, and the tDQSCK is a parameter representing a skew of the data strobe signal DQS and the clock CLK.
These are not only related to a data pattern, but also related to the fact that a power noise, which is generated at the data input/output pads DQ due to the ringing back effect and the like, affects the data strobe signal pads DQS and DQSB.